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7. A D flip-flop has a condition of D= 1, CLK = 0, Q = 1, and PRE is inactive. If a 100 Hz clock pulse is applied to the CLR, the output Q will be (a) o (b) 1 (c) 100 Hz (d) 200 Hz (e) 50 Hz 8. A D flip-flop has a condition of D=0, Q = 0, and both PRE and CLR are inactive. If a 100 Hz clock pulse is applied to CLK, the output Q will be (a) 0 (b) 1 (c) 100 Hz (d) 200 Hz (e) 50 Hz 9. A D flip-flop has a condition of CLK = 1, Q=1, and both PRE and CLR are inactive. If a 100 Hz clock pulse is applied to D, the output Q will be (a) 0 (b) 1 (C) 100 Hz (d) 200 Hz (e) 50 Hz

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